<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom">
  <channel>
    <title>Kai Weng — Tech Blog</title>
    <link>https://windandfall.me</link>
    <description>Personal technical blog about digital IC design, computer architecture, FPGA, and AI chips.</description>
    <language>en</language>
    <lastBuildDate>Wed, 27 May 2026 11:22:21 GMT</lastBuildDate>
    <atom:link href="https://windandfall.me/feed.xml" rel="self" type="application/rss+xml"/>
    
    <item>
      <title><![CDATA[Cache Coherence Protocols: From MSI to MOESI — A Hardware Designer's Perspective]]></title>
      <link>https://windandfall.me/blog/cache-coherence-primer</link>
      <guid isPermaLink="true">https://windandfall.me/blog/cache-coherence-primer</guid>
      <description><![CDATA[Deep dive into cache coherence protocols for shared-memory multiprocessors. We trace the evolution from simple MSI to complex directory-based MOESI, with RTL implementation considerations.]]></description>
      <pubDate>Sat, 15 Mar 2025 00:00:00 GMT</pubDate>
      <category>Cache</category>
      <category>Computer Architecture</category>
      <category>SystemVerilog</category>
      <category>Verification</category>
    </item>
    <item>
      <title><![CDATA[Designing a Systolic Array for Neural Network Inference: Architecture Deep Dive]]></title>
      <link>https://windandfall.me/blog/npu-systolic-array-design</link>
      <guid isPermaLink="true">https://windandfall.me/blog/npu-systolic-array-design</guid>
      <description><![CDATA[A practical guide to designing systolic array accelerators for neural network inference, covering dataflows, memory hierarchy, and PE microarchitecture.]]></description>
      <pubDate>Mon, 20 Jan 2025 00:00:00 GMT</pubDate>
      <category>NPU</category>
      <category>AI Chip</category>
      <category>Systolic Array</category>
      <category>Computer Architecture</category>
    </item>
    <item>
      <title><![CDATA[Real-Time FMCW Radar Processing on FPGA: Signal Chain Design and Implementation]]></title>
      <link>https://windandfall.me/blog/fpga-radar-signal-processing</link>
      <guid isPermaLink="true">https://windandfall.me/blog/fpga-radar-signal-processing</guid>
      <description><![CDATA[End-to-end FPGA implementation of FMCW radar signal processing: 2D FFT, CFAR detection, and angle estimation on Xilinx Zynq. Complete with Verilog RTL examples and MATLAB verification.]]></description>
      <pubDate>Fri, 08 Nov 2024 00:00:00 GMT</pubDate>
      <category>FPGA</category>
      <category>Radar</category>
      <category>Verilog</category>
      <category>Signal Processing</category>
      <category>Zynq</category>
    </item>
    <item>
      <title><![CDATA[Building a RISC-V Out-of-Order Core: Pipeline Design, Branch Prediction, and Memory Ordering]]></title>
      <link>https://windandfall.me/blog/riscv-o3-core-design</link>
      <guid isPermaLink="true">https://windandfall.me/blog/riscv-o3-core-design</guid>
      <description><![CDATA[A hands-on guide to designing an out-of-order RISC-V processor core, from the frontend fetch stage through the issue queue to the load-store unit and ROB commit.]]></description>
      <pubDate>Thu, 22 Aug 2024 00:00:00 GMT</pubDate>
      <category>RISC-V</category>
      <category>SystemVerilog</category>
      <category>Computer Architecture</category>
      <category>Processor Design</category>
    </item>
  </channel>
</rss>