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Latest Articles
Thoughts on chip design and computer architecture
Computer Architecture
March 15, 2025Cache Coherence Protocols: From MSI to MOESI — A Hardware Designer's Perspective
Deep dive into cache coherence protocols for shared-memory multiprocessors. We trace the evolution from simple MSI to complex directory-based MOESI, with RTL implementation considerations.
Cache
Computer Architecture
AI Chips
January 20, 2025Designing a Systolic Array for Neural Network Inference: Architecture Deep Dive
A practical guide to designing systolic array accelerators for neural network inference, covering dataflows, memory hierarchy, and PE microarchitecture.
NPU
AI Chip
FPGA
November 8, 2024Real-Time FMCW Radar Processing on FPGA: Signal Chain Design and Implementation
End-to-end FPGA implementation of FMCW radar signal processing: 2D FFT, CFAR detection, and angle estimation on Xilinx Zynq. Complete with Verilog RTL examples and MATLAB verification.
FPGA
Radar